This invention relates to high voltage MOS transistors. More particularly, this invention relates to apparatus and methods for forming an MOS transistor with a substrate implant to achieve various combinations of low threshold voltage, high breakdown voltage, and transistor operation at high voltages without experiencing vertical punch-through.
Many applications for semiconductor devices require transistors that are isolated from the substrate and that can operate at high voltages (e.g., greater than 40 volts). Applying a high voltage to a transistor can cause several problems. For example, a high voltage at the drain can cause vertical punch-through in an NMOS transistor with an P-type substrate and in a PMOS transistor with an N-type substrate. Vertical punch-through can cause unwanted current flow between the drain and the buried layer at high drain voltages.
One previously known high voltage DMOS transistor 10 is shown in FIG. 1A. DMOS transistor 10 has a grounded body and a high threshold voltage. DMOS transistor 10 includes highly doped N-type (i.e., N+) source region 12, N+ drain region 14, P-type body region 16, gate 15, N-type drain region 13 of an N-type epitaxial layer, and P-type substrate 17. N-type drain region 13 is tied electrically to N+ drain region 14 (because both regions are N-type) to form an extension of the drain. Thick oxide layer 18 lies between gate 15 and N-type drain region 13. This configuration reduces the impact generation rate of carriers by reducing the electric field in the drain at high drain voltages. However, thick oxide layer 18 causes DMOS transistor 10 to have undesirably large device dimensions. Thick oxide layer 18 also increases the drain-to-source resistance (RDS-ON) which is also undesirable, because thick oxide 18 encroaches down into N-type drain region 13. A further disadvantage of transistor 10 is that the N-type doping concentration in N-type drain region 13 is higher near bird""s beak 18A of thick oxide 18 than the N-type doping concentration near the lower boundary 18B of thick oxide 18. This effect causes an increased electric field under the gate which is also undesirable.
A further disadvantage of DMOS transistor 10 is that it cannot be used as a pass transistor, particularly a high voltage pass transistor. A pass transistor is a device in which the source and the drain regions are interchangeable and preferably symmetrical. In a pass transistor, the source, drain, and body regions must be isolated from the substrate. Furthermore, in a high voltage pass transistor, the body region cannot be tied electrically to either the source or the drain. Transistor 10 does not meet these criteria, because its source (region 12) and drain (region 14 and a portion of layer 13) are not symmetrical, body region 16 is tied electrically to the source, and body region 16 is tied electrically to substrate 17. Further features of the DMOS transistor with grounded body are described in an article by Parpia et al., entitled xe2x80x9cA CMOS Compatible High-Voltage IC Process,xe2x80x9d IEEE Transactions on Electron Devices, Vol. 35, No. 10, October 1988, pp. 1687-1694.
Another previously known high voltage DMOS transistor 20 with an isolated body is shown in FIG. 1B. DMOS transistor 20 includes highly doped N-type (i.e., N+) source region 22, N+ drain region 27, P-type body region 24, gate 21, thick oxide 25, P-type epitaxial layer 26, P-type substrate 29, N-type well 23 in P-epitaxial layer 26, and highly doped N+ buried layer 28. N+ buried layer 28 isolates substrate 29 from body region 24 to prevent current flow between these two regions. However, N+ buried layer 28 is tied electrically to drain region 27 through N-well 23. Therefore, the output capacitance at the drain is undesirably high because N+ buried layer 28 has a wide area. High output capacitance is undesirable because it slows down the frequency of the transistor""s output signal. Furthermore, DMOS transistor 20 cannot be used as a pass transistor, because the source (region 22) and the drain (including regions 27 and 23) are not symmetrical, and body region 24 is tied electrically to the source at P+ region 19. Further features of the DMOS transistor with isolated body are described in an article by Tsui et al., entitled xe2x80x9cIntegration of Power LDMOS into a Low-Voltage 0.5 xcexcm BiCMOS Technology,xe2x80x9d IEDM Digest, 1992, pp. 27-30.
Yet another previously known high voltage MOS transistor 30 is shown FIG. 1C. Transistor 30 has high voltage P-type well 35 that forms the body region of the device in N-type epitaxial layer 42. N-type extension regions 36 and 38 in P-well 35 form extensions of the drain and source regions. Transistor 30 also has highly doped N-type regions 32 and 34. Regions 32/36 and regions 34/38 are symmetrical and may be used interchangeably as drain and source regions of transistor 30. Transistor 30 also has N+ buried layer 40 that is not tied electrically to the drain as shown in FIG. 1C. In transistor 30, vertical punch-through between the drain and buried layer 40 can occur when the depletion regions of the drain and N-epitaxial layer 42 merge in P-well 35 at high drain voltages. For example, if regions 32 and 36 form the drain, then vertical punch-through can occur when the depletion region of the N-extension 36 PN junction in P-well 35 meets the depletion region of the N-epitaxial layer 42 PN junction in P-well 35. The output capacitance of transistor 30 is high during vertical-punch-through because the drain and buried layer 40 become electrically coupled together.
To prevent vertical punch-through in transistor 30, two parameters may be changed. First, the doping concentration of P-well body 35 may be increased (e.g., 4-5xc3x971012 cmxe2x88x922) to reduce expansion of the drain and buried layer depletion regions at high voltages. High doping in body region 35 causes the undesirable effects of increasing the threshold voltage of the transistor and reducing the breakdown voltage at the drain-to-body junction. Secondly, the depth of body region 35 and the thickness of epitaxial layer 42 may be increased so that the depletion regions do not merge at high voltages.
Because the drain and epitaxial layer depletion regions at 40 volts are each about 3.3 microns (micrometers) thick for MOSFETs, the thickness of the epitaxial layer must be greater than 6 microns. A vertical NPN bipolar junction transistor (BJT) with a breakdown voltage of 40 volts requires only about 4 microns of epitaxial thickness. In BiCMOS processes a uniform epitaxial layer is used for MOSFETs and BJTs (bipolar junction transistors). Because the MOSFETs must have an epitaxial thickness of at least 6 microns to operate properly, the thickness of all of the devices formed in the same wafer including the BJTs must be at least 6 microns to achieve isolation. A thicker epitaxial layer undesirably reduces fT (the frequency at which the current gain goes to unity), causes a higher VCE-SAT (collector-emitter saturation voltage), and causes a higher collector resistance for the BJTs.
A further technique for reducing the threshold voltage in high voltage transistors involves using retrograde wells. A retrograde well is a region of doped silicon that has a doping concentration which decreases toward the surface of the well. The retrograde well may be used for the body of the transistor to achieve a reduced threshold voltage. FIG. 2A is a graph of the doping concentration along a vertical cross section below the gate oxide of an NMOS device with a retrograde P-type well formed in an N-type epitaxial layer on a P-type substrate with a highly doped N-type buried layer. In FIG. 2A, solid lines 44 represent the concentration of P-type dopants, and dotted line 46 represents the concentration of N-type dopants. FIG. 2B is a graph of the doping concentration along a vertical cross section below the gate oxide of an NMOS device with a retrograde P-type well formed in a P-type epitaxial layer on a P-type substrate with a highly doped N-type buried layer. In FIG. 2B, solid line 47 represents the concentration of P-type dopants and dotted line 48 represents the concentration of N-type dopants.
A retrograde P-well may be formed using Boron diffusion followed by surface oxidation in order to reduce the Boron doping concentration at the surface of the well. However, the reduction in the P-type doping concentration at the surface of the retrograde well is typically not adequate to achieve the desired reduction in surface concentration to achieve a sufficient reduction in the threshold voltage and protection against vertical punch-through. For example, a reduction of 4-8 times in the P-type doping concentration at the surface of the retrograde well is typically required.
Retrograde wells may also be achieved using high-energy, deep ion implantation. However, for high voltage ( greater than 20 V) applications, the peak doping concentration of the retrograde well must be high enough to prevent vertical punch-through. In addition, the highly concentrated dopants must be deep enough in the epitaxial layer so that the breakdown voltage of the transistor is not reduced. More than 400 KeV of implantation energy is required to implant the peak doping concentration deep enough into the epitaxial layer so that breakdown voltage criteria are achieved while taking into account diffusion of the implanted dopants. High energy implanters are therefore required for this process. These tools are not commonly available and are extremely expensive.
It would, however, be desirable to provide a transistor that has a thin epitaxial layer and that can operate a high voltage without experiencing vertical punch-through or breakdown. It would further be desirable to provide a high voltage MOS transistor having a low threshold voltage. It would also be desirable to provide a high voltage MOS transistor that can be fabricated with low-voltage CMOS and BiCMOS processes. It would also be desirable to provide a high-voltage MOS transistor that has a symmetrical structure and that is fully isolated from the substrate so that it can operate effectively as a pass transistor.
It is an object of the present to provide an MOS transistor that has a thin epitaxial layer and can operate at high voltages without experiencing vertical punch-through or breakdown.
It is also an object of the present invention to provide an MOS transistor with a low threshold voltage.
It is a further object of the present invention to provide a high voltage MOS transistor that is compatible with low-voltage sub-micron CMOS and BiCMOS processes.
It is a further object of the present invention to provide a high voltage MOS transistor that has a symmetrical structure and that is fully isolated from the substrate so that it can operate as a pass transistor.
These and other objects of the present invention are provided by high-voltage MOS transistors having substrate implants. In a preferred embodiment, the MOS transistor has an up-retro well extending from a buried layer in the substrate into the epitaxial region of the transistor. The present invention also includes methods for forming MOS transistors with a substrate implant. In a preferred embodiment of the present invention, dopants are implanted and driven into the substrate of a semiconductor wafer to form a highly doped buried layer. Additional dopants are then implanted into the substrate to form an up-retro well. An epitaxial layer is then formed on the substrate. The up-retro well dopants diffuse up from the substrate into the epitaxial layer to form an up-retro well region. The up-retro well dopants have a high diffusivity so that they diffuse up into the epitaxial layer beyond the buried layer.
The up-retro well prevents vertical punch-through and breakdown, and allows for a low threshold voltage in high voltage MOS transistors. High voltage MOS transistors with an up-retro well may be formed in a semiconductor wafer that has a thin epitaxial layer. Also, high voltage MOS transistors of the present invention can be used as pass transistors because the source and drain regions may be used interchangeably. High-voltage MOS transistors of the present invention may be fabricated using processes that are standard in low voltage sub-micron CMOS and BiCMOS process technology.